Fast approximately timed simulation

International audienceIn this paper we present a technique for fast approximately timed simulation of software within a virtual prototyping framework. Our method performs a static analysis of the program control flow graph to construct annotations of the simulated program, combined with dynamic performance information. The static analysis estimates execution time based on a target architecture model. The delays introduced by instruction fetch and data cache misses are evaluated dynamically. At the end of each block, static and dynamic information are combined with branch target prediction to compute the total execution time of the blocks. As a result, we can provide approximate performance estimates with a high simulation speed that is still usable for software developers

Designing a CPU model: from a pseudo-formal document to fast code

For validating low level embedded software, engineers use simulators that take the real binary as input. Like the real hardware, these full-system simulators are organized as a set of components. The main component is the CPU simulator (ISS), because it is the usual bottleneck for the simulation speed, and its development is a long and repetitive task. Previous work showed that an ISS can be generated from an Architecture Description Language (ADL). In the work reported in this paper, we generate a CPU simulator directly from the pseudo-formal descriptions of the reference manual. For each instruction, we extract the information describing its behavior, its binary encoding, and its assembly syntax. Next, after automatically applying many optimizations on the extracted information, we generate a SystemC/TLM ISS. We also generate tests for the decoder and a formal specification in Coq. Experiments show that the generated ISS is as fast and stable as our previous hand-written ISS.Comment: 3rd Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (2011

Unification d'arborescences : évaluation sémantique d'énoncés en langue naturelle

Universités : Université scientifique et médicale de Grenoble et Institut national polytechnique de GrenobleElaboration d'un algorithme d'unification après présentation de la notion de ramification. Cet algorithme peut aussi être utilisé dans le cadre de la transformation de programmes. Puis étude d'un système d'analyse linguistique dans lequel est intégré l'algorithme

SimSoC: A SystemC TLM integrated ISS for full system simulation

International audienceThe development of embedded systems requires the development of increasingly complex software and hardware platforms. Full system simulation makes it possible to run the exact binary embedded software including the operating system on a totally simulated hardware platform. Whereas most simulation environments do not support full system simulation, or do not use any hardware modeling techniques, or have combined different types of technology, SimSoC is developing a full system simulation architecture with an integrated approach relying only upon SystemC hardware modeling and transaction-level modeling abstractions (TLM) for communications. To simulate processors at reasonably high speed, SimSoC integrates instruction set simulators (ISS) as SystemC modules with TLM interfaces to the other platform components. The ISSpsilas use a variant approach of dynamic translation to run binary code. The dynamic translator uses pre-compiled code that consists of specialized functions for instruction execution, using partial evaluation techniques. It is generated by a configurable code generator, which makes it possible to tune the generated code to optimize simulation speed for the target software application

Flexible Runtime Verification Based On Logical Clock Constraints

International audienceWe present in this paper a method and tool for the verification of causal and temporal properties of embedded systems, by analyzing the trace streams resulting from virtual prototypes that combines simulated hardware and embedded software. The proposed method makes it possible to analyze different kinds of properties without rebuilding the simulation models. Logical clocks are used to identify relevant points to put observation probes and thus also reducing the trace streams size. We propose a property specification language, called PSML, and based on behavioral patterns that does not require knowledge of temporal logics. From a given PSML specification, simulation is instrumented to generate a trace and the code is dynamically loaded by the simulator. The resulting trace stream is analyzed by parallel automata generated from the specification. The experiments, developed over the SimSoC virtual prototyping framework, show flexibility, possibility of using multi-core platforms to parallelize simulation and verification, providing fast results

PSCV: A Runtime Verification Tool for Probabilistic SystemC Models

International audienceThis paper describes PSCV, a runtime verification tool for a class of SystemC models which have inherent probabilistic characteristics. The properties of interest are expressed using bounded linear temporal logic. The various features of the tool including automatic monitor generation for producing execution traces of the model-under-verification, mechanism for automatically instrumenting the model, and the interaction with statistical model checker are presented

Automated Generation of Instruction Set Simulator from Specification

International audienceWe present here an architecture compiler, namely a software that takes as input the description of a processor architecture as it is available from the vendors on their web site, and generates an instruction set simulator for that processor, which can be readily integrated into a simulation framework. This architecture compiler extracts relevant information from the .pdf file, translated into an XML specification. After further XML transformations, the C++ code of the simulator is finally generated. The paper details the approach and the results for the ARM Version 7 processor, that is suitable for other architectures as well

SimSoC: A full system simulation software for embedded systems

International audienceThe development of embedded systems requires the development of increasingly complex software and hardware platforms. Full system simulation makes it possible to run the exact binary embedded software including the operating system on a totally simulated hardware platform. Whereas most simulation environments do not support full system simulation, or do not use any hardware modeling techniques, or have combined different types of technology, SimSoC is developing a full system simulation architecture with an integrated approach relying only upon SystemC hardware modeling and transaction level modeling abstractions (TLM) for communications. To simulate processors at reasonably high speed, SimSoC integrates instruction set simulators (ISS) as SystemC modules with TLM interfaces to the other platform components. The ISS's use a variant approach of dynamic translation to run binary code. The paper describes the overall architecture of the SimSoC full system simulator, a description of the ISS implementation and integration with some other components. The final section reports results obtained, in particular simulation of an existing System On Chip that can run the Linux operating system

TRAP: trace runtime analysis of properties

International audienc